This Invention relates to an improved method for the manufacture of thin film transistors (TFTs) and, more particularly, to a method for the manufacture of fully self-aligned TFTs wherein back illumination is utilized to accomplish the configuration of TFT contact regions and metallization.
TFTs, using hydrogenated amorphous silicon (a-Si:H) as the active material, are widely used in large area electronics applications e.g., active matrix liquid crystal displays (AMLCDs). A typical AMLCD addressing scheme is shown in FIG. 1. There, a TFT T is used to charge each pixel capacitance C to a voltage specified by the video signal. Since the TFT controls the charging voltage, improvements in display size, greyscale, and resolution depend on maximizing TFT performance and minimizing parasitic effects associated with the staggered-inverted TFT structure that is typically used for AMLCDs (see FIG. 2).
TFT 10 comprises a glass substrate 12 on which a gate electrode 12 has been deposited. A silicon nitride layer 14 is positioned between gate electrode 12 and a thin semiconductor layer 18 of hydrogenated amorphous silicon (a-Si:H). Source and drain interface layers 20 and 22 are comprised of n+ doped a-Si:H and are covered by metallization layers 24 and 26, respectively. The distance L defines the approximate conduction channel length within active layer 18.
Self-aligned (SA) TFT structures have been of interest for several years because they benefit performance and minimize parasitic effects. Such structures can allow a TFT conduction channel length L reduction which increases the capacitance charging currents, and a minimization of contact overlap which reduces the TFT parasitic capacitance. Previously demonstrated SA-TFT structures have not been widely adopted in display manufacturing, though, because they require more complicated manufacturing processes.
Though SA-TFTs have been demonstrated for a-Si:H TFTs, previous SA-TFTs have had the disadvantage of increased process complexity, limited device performance, or both. The two most common staggered-inverted TFT structures are the back-channel etched TFT (BCE-TFT) and the tri-layer/i-stopper TFT. The standard BCE-TFT usually requires fewer processing steps than a conventional tri-layer TFT process, but involves a critical etch step that limits the minimum a-Si:H thickness- which, in turn, limits the device performance. Tri-layer TFTs typically have better electrical performance, but require an additional material deposition step and an additional photolithography mask step.
The self-aligned BCE-TFT process is described by Busta et al. in xe2x80x9cSelf-Aligned Bottom Gate Submicrometer Channel Length a-Si:H Thin Film Transistorsxe2x80x9d Trans. On Electron Devices, Vol. 36, No. 12, pp 2883-2888, 1989. FIG. 3 shows the process for making such a self-aligned BCE-TFT. The process allows channel length minimization (determined only by the minimum gate dimension), but requires relatively thick ( greater than xcx9c60 nm) a-Si:H layers. Since very thin a-Si:H layers can improve TFT extrinsic mobility, thicker a-Si:H layers constrain the self-aligned BCE-TFT performance.
To achieve self-alignment for high-performance TFTs, fully self aligned (FSA) tri-layer TFT processes have also been demonstrated. FIG. 4 shows a method for fabricating FSA tri-layer TFTs using an ion shower doping step. While this process does result in a minimum channel length determined only by a minimum gate dimension, and the increased performance associated with tri-layer devices, it requires an ion doping process which has not been used in AMLCD manufacturing, and is not commercially available for large area applications.
Another method for fabricating SA tri-layer TFTs is shown in FIG. 5. Instead of using an ion shower doping step, additional photolithography mask steps are used to define contact regions of the TFT, allowing a deposited n+ contact layer to be used. Though this process can be used to fabricate semi-SA tri-layer TFTs, the additional mask steps result in a minimum channel length that is determined by not only the gate dimension, but also the contact region alignment tolerances and the minimum spacing of the contact photolithography.
Accordingly, it is an object of the invention to produce an FSA tri-layer TFT wherein channel length is determined by minimum photolithographic dimensions and not by contact region alignment tolerances.
It is a further object of the invention to produce an FSA tri-layer TFT wherein contact region placement is a direct function of gate electrode placement.
The method of the invention configures a tri-layer thin film transistor (TFT) on a substrate, the TFT including a stack including a gate electrode supported by the substrate, followed by a first layer of insulator, a layer of semiconductor and a second layer of insulator. The method employs a first step of illumination through the substrate, as shadowed by said gate electrode, to enable a patterning of the second layer of insulator into an insulator patch which is aligned with the gate electrode. A next step of illumination through the substrate, as shadowed by said gate electrode, and using a photolithographic mask, enables a patterning of metallization contacts for the TFT in alignment with the insulator patch.